A peak current mode control (PCMC) is a control scheme for power converters enabling, in theory, certain desirable advantages like voltage feed forward, automatic cycle by cycle current limiting and other advantages known to persons skilled in the art. To implement this PCMC control scheme in practice, precisely controlled pulse width modulated (PWM) waveforms to drive control switches in power converters are essential. These power converters often employ a peak current reference without or with slope compensation. The peak current reference is compared with a current sensed at the output of the power converter; the result of the comparison controlling the PWM waveform.
FIG. 1A depicts a conceptual block diagram of a digitally controlled PCMC based power converter system 100. A power converter 102 receives at its input an input voltage Vin from a source 104 and provides at its output a regulated voltage Vout to a load 106. To accomplish the Vout regulation, the Vout feedback is provided to block 108 comprising an analog-to-digital (ADC) converter, which digitizes the Vout feedback, which is then provided to a first input of a block 110 comprising a comparator and a voltage controller (not shown). A digital reference voltage Vref from a reference voltage source 112 is provided to a second input of the block 110. The digitized Vout—d feedback and the digital reference voltage Vref are compared by the comparator and the result of the comparison is provided to the voltage controller. Based on the comparison, the voltage controller generates voltage Vcomp, which is provided at the output of the voltage controller 110 and serves to derive a peak current reference signal Ipref.
It is well known by persons of ordinary skills in the art that PCMC based power converter systems suffer from stability issues and sub-harmonic oscillations for operation above 50% duty cycle theoretically. A duty cycle is the time that the PWM waveform spends in an active state. Consequently, the PCMC based power converter systems may implement a slope compensation. The slope compensation can be applied to the peak current Ipeak, decrementing the peak current Ipeak by a ramp thus arrive at a slope compensated peak current reference signal Ipref. Alternatively, the slope compensation may be achieved by keeping the peak current Ipeak constant and increment a feedback current Ifb by the ramp.
As depicted in FIG. 1A, the feedback current Ifb is sensed at a node of converter 102 dependent on a topology of power converter, means of controlling the converter, and other design criteria known to persons skilled in the art. By means of example, the feedback current may be a current through the load 106, it could be a current through an inductor, transformer primary current, and other nodes known to persons skilled in the art.
For clarity of explanation of the different aspects the slope compensated peak current reference signal Ipref is used; however, the disclosed concepts are equally applicable to the case where slope compensation ramp is added to the feedback current Ifb.
The generation of a slope compensated peak current reference signal Ipref is carried out by a block 114, comprising a digital-to-analog (DAC) converter, for converting the digital representation of the voltage Vout provided by the voltage controller 114 to an analog representation corresponding to a peak current Ipeak, and a ramp generator which generates a slope for compensation taking the value of the a peak current Ipeak as initial value for the ramp generator.
The slope compensated peak current reference signal Ipref is provided to a first input of a block 116. The second input of the block 116 is provided with a feedback current Ifb corresponding to a sensed current in the power converter 102. The block 116 comprises a comparator (not shown), which compares the slope compensated peak current reference signal Ipref with the feedback current Ifb, and the result of the comparison affects various attributes of the PWM waveforms PWM(1)-PWM(n) generated by a PWM generator (not shown) of the block 116 and provided to the power converter 102.
Although as described above, blocks 108, 110, 114, 116, and 112 comprise a digital PCMC controller 101, persons skilled in the art would understand that not all the blocks need to be implemented in the digital PCMC controller 101. By means of an example, the slope compensation, i.e., block 114 may or may not be implemented in the digital PCMC controller 101. Likewise, the comparator, described as a part of block 116, may be external to the digital PCMC controller 101. The digital PCMC controller 101 may optionally be interfaced with or reside inside a digital controller 117, e.g., a Microcontroller, Digital Signal Processor, and any other digital controller known to persons of ordinary skills in the art. The digital controller 117 may be utilized to program various attributes of the PWM waveforms and the slope for compensation; therefore, imparting more intelligence to the system and an ability to adaptively adjust to changing conditions for optimum digitally controlled PCMC based power converter system 100 performance.
The different implementation of the digital PCMC controller 101 may provide a different number of the PWM waveforms in accordance with a proposed use of a particular digital PCMC controller 101. However, it is understood by persons of ordinary skills in the art that not all the waveforms need to be generated and provided to the power converter. Thus, by means of an example a buck power converter may require a single PWM waveform, a synchronous buck power converter may require two PWM waveforms, an isolated phase shifted full bridge direct-current-to-direct-current (DC-DC) converter with synchronous rectification may require six waveforms, and the like.
FIG. 1B depicts an amplitude as a function of time of waveforms of interest regarding block 116. For clarity of explanation and without any loss of generality, only a single PWM waveform is considered; however, the disclosed aspects are equally applicable to a plurality of PWM waveforms.
The PWM period starts at time t0, when the PWM generator 116(2) causes the PWM waveform 118 transitions from a first value A1 to a second value A2. In response the power converter 102 causes a flow of a feedback current Ifb, and the feedback current Ifb 120, provided to the non-inverting input of a comparator 116(1), starts increasing from a value Ii. The slope compensated peak current reference signal Ipref 122, provided to the inverting input of a comparator 116(1), starts decreasing from a value Ipeak. Although the slope compensated peak current reference signal Ipref 122 is depicted as a linearly decreasing, persons skilled in the art will understand that non-linearly decreasing slope compensated peak current reference signal Ipref 122 is within the scope of the disclosure.
At time t1, the value of the sensed current through the load Ifb 120 and the value of the slope compensated peak current reference signal Ipref 122 became equal, which causes a change of the output of the comparator 116(1), which in turn causes the PWM generator 116(2) to transition PWM waveform 118 from a second value A2 to a first value A1. In response, the feedback current Ifb 120 starts decreasing.
At time t2, the PWM period ends, and the cycle is repeated.
The digitally controlled PCMC based power converter system 100 is subject to predictable noise, e.g., switching noise from PWM waveforms, switching noise from relays, non-switching digital noise, and other noises generated by the digitally controlled PCMC based power converter system 100. As well understood by persons skilled in the art, the switching noise is a result of fast transition of a signal from one amplitude to another amplitude. Although the predictable noise affects all the circuitry of the digitally controlled PCMC based power converter system 100, proper design and filtering of the circuitry comprising the slope compensated peak current reference signal Ipref 122 reduces the level of the predictable noise to negligible levels. However, such a level of filtering cannot be applied to the feedback current Ifb 120, because to reduce the level of the predictable noise to negligible levels would cause severe distortion of the transition edges of the PWM waveforms; therefore, negatively affect a performance of the digitally controlled PCMC based power converter system 100. Accordingly, in practice, some predictable noise may be present.
It is noted that in FIG. 1B, both the slope compensated peak current reference signal Ipref 122 and the feedback current Ifb 120 are idealized waveforms, at least in that no predictable noise is present. Consequently, the output of the comparator 116(1) provided to the PWM generator 116(2) results in a correctly timed PWM duty cycle 122 at the output the PWM generator 116(2). A duty cycle is the time that the PWM waveform spends in an active state, in this case at the second value A2 as a fraction of the PWM period.
As described supra, and depicted in FIG. 1C, the PWM waveform 118 transitions from a first value A1 to a second value A2 at the beginning of the PWM period; therefore, causing the predictable switching noise 120(1) at the beginning of the PWM period. If/when a magnitude of this noise is greater than or equal to the slope compensated peak current reference signal Ipref 122, the output of the comparator 116(1) changes, which is reflected on the input of the PWM generator 116(2) and results in an incorrectly timed PWM waveform 118 of the PWM generator 116. Consequently, incorrect power is delivered by the power converter 102 to the load 106.
FIGS. 1A-1C and associated text are simplified for the purpose of clarity of explanation. Consequently, in a more complex power converter, e.g., the above-mentioned isolated phase shifted full bridge direct-current-to-direct-current (DC-DC) converter with synchronous rectification, which requires six PWM waveforms to be generated by the digital PCMC controller, the point in time where the periodic/predictable noise occurs relative to the PWM period as well as the periodic/predictable noise duration may change with changing operating conditions, e.g., input and/or output voltage, load, and other operating conditions, as well as with parameters of the digitally controlled PCMC based power converter system, e.g., temperature. Furthermore, there may be more than a single switching noise in the PWM period. By means of an example, in the isolated phase shifted full bridge direct-current-to-direct-current (DC-DC) converter with synchronous rectification a switching noise occurs twice in the PWM period.
Based on the foregoing, there is a need in the art to avoid this incorrect and undesirable situation in power converters, by implementing selective blanking